Intel will release 45nm CMOS SRAM chip
Intel will release SRAM with 45nm high-k metal gate on ISSCC 2008, which is mainly used for the secondary cache of the new generation "Core2" microprocessor. The topic of the speech at the meeting was "a 153mb SRAM design with dynamic stability enhancement and leakage reduction in 45nm high-k metal gate CMOS technology"
when the power supply voltage of SRAM to be released is 1.1V, the operating frequency is 3.5GHz. Through the dynamic body bias control of the PMOS transistor of the cell, improving the stability of the SRAM cell is also a test for the strength of the experimenter. At the same time, the leakage current is controlled by programming
before the 65nm LSI, the transistor gate insulating film of logic LSI manufacturers has been made of silicon materials. However, with the development of process miniaturization to 45nm, people are more and more worried that the leakage current will increase sharply while the thickness of gate insulation film is decreasing. By using high-k insulating film, the leakage current can be reduced and the performance of LSI can be improved
third, Intel's improvement on transistors comes from the use of many previous crystals and the adoption of bar body tube gate media affected by shear stress in product design. Intel uses a compound based on hafnium to replace the previous method and logic of vibration testing, and continuously improves silicon dioxide. This high-k medium based on hafnium has good insulation properties, At the same time, a high-k field effect can be formed between the gate and the silicon substrate. High-k hafnium compounds are thicker than silicon dioxide and maintain ideal high field effect characteristics. Therefore, this high-k material can also greatly reduce leakage current. According to the official data released by Intel, this high-k medium can reduce the leakage current by more than 10% compared with the previous silicon dioxide material. At the same time, because of the improvement of the field effect, the driving current from the source to the drain of the transistor is increased by 20%, and the leakage current from the source to the drain is reduced by more than 5 times. If these data are really the same as those published by Intel, we can obtain higher switching efficiency and lower leakage current for a single transistor than before. For modern processors with hundreds of millions of transistors, we can benefit a lot from it, which is obviously more conducive to improving the performance per watt of Intel processors
although this high-k gate dielectric based on hafnium has good characteristics of high field efficiency and insulation, it cannot use the previous polysilicon gate, but needs to be replaced by a new metal gate. At present, Intel has not disclosed the constituent elements of these materials and their specific formula, but Intel representatives said at the previous new transistor presentation, Competitors who want to achieve the efficiency of the current Intel 45nm product transistors need at least to go to the competitor's next-generation 32nm process. We hold an attitude to Intel that needs to be investigated. After all, the actual performance needs to wait for the specific release of the products of both sides before we have a correct answer
the 55th ISSCC Conference (isscc2008) will be held in San Francisco from February 3 to 7 next year. A paper on PLL submitted by Institute of microelectronics, Tsinghua University was selected
the title of the paper is "a 1GHz fractional-N PLL clock generator with low OSR ΔΣ Modulation and FIR-Embedded Noise Filtering”。 According to the ISSCC data, the fractional frequency PLL clock generator with 1ppm frequency accuracy is realized by using 0.18um CMOS technology in this paper. The use of hybrid fir noise filtering technology makes the out of band quantization error reduced to a new low, thus realizing a low oversampling rate ΔΣ Modulation